1. Field
Exemplary embodiments of the present invention relate to an integrated circuit chip, and more particularly, to a technology for setting an optimal latency for the performance of an integrated circuit chip.
2. Description of the Related Art
Integrated circuit chips communicate with neighboring chips by transmitting or receiving data or signals from neighboring chips. For example, when a memory controller applies a read command to a memory, the memory transfers stored data to the memory controller. Here, the memory may output the data to the memory controller with a delay, where, in response the read command, the delay may occur in retrieving the stored data and preparing for being output.
When a chip A and a chip B interact with each other, the chip A requests the chip B to perform a desired operation. There is a delay until the chip B performs the operation in response to the request from the chip A. This delay is referred to as latency. For example, when a CAS latency CL is set to 7 for commands between a memory and a memory controller and the memory controller applies a read command to the memory, the memory transfers a data to the memory controller after 7 clocks from the time that the read command is applied.
According to a recent trend, integrated circuit chips may operate may operate at several power supply voltage levels. However, when the power supply voltage for the operation of an integrated circuit chip is changed, the operation speed of the integrated circuit chip may change. Here, it is useful to optimally set the latency between chips despite changes in operation speeds.